Terabit Burst Switching Progress Report (3/98–6/98)

This report summarizes progress on Washington University’s Terabit Burst Switching Project, supported by DARPA and Rome Air Force Laboratory. This project seeks to demonstrate the feasibility of Burst Switching, a new data communication service which can more effectively exploit the large bandwidths becoming available in WDM transmission systems, than conventional communication technologies like ATM and IP-based packet switching. Burst switching systems dynamically assign data bursts to channels in optical data links, using routing information carried in parallel control channels. The project will lead to the construction of a demonstration switch with throughput exceeding 200 Gb/s and scalable to over 10 Tb/s. This work is supported by the Advanced Research Projects Agency and Rome Laboratory (contract F30602-97-10273). Terabit Burst Switching Progress Report (3/98–6/98) Jonathan S. Turner [email protected] This report summarizes progress on the Terabit Burst Switching Project at Washington University for the period from March 15, 1998 through June 15, 1998. Efforts during this period have concentrated on developing a detailed understanding of the control issues associated with the burst handling process. We have also continued the engineering efforts on the ATM switch and begun to address the interconnection of ATM and burst switches. 1. Prototype Burst Switch Plans Figure 1 shows the planned configuration for the burst switch prototype. The system will include six I/O modules each capable of terminating a burst data link with 32 channels. For budgetary reasons, the different channels will be carried on separate fibers rather than on WDM channels in a single fiber. However, the prototype will treat the collection of fibers constituting a single “link” exactly as it would if they were carried on a single fiber. Each I/O module will contain the optics and transmission electronics for terminating 32 channels. We have tentatively selected 12 channel VCSEL-based components from Siemens for the optics, and a four channel transmission component from Vitesse (compatible with Fibre Channel) for the transmission line coding and clock recovery functions. In addition to these components, the I/O module will contain a four channel synchronization chip whose principal function is to delay data received from the link for a fixed time period before forwarding it to the interconnection network. The control section of the I/O module includes a Time Stamp Component, an ATM Input Port Processor, an ATM Output Port Processor and a Burst Processor. The interconnection network for the prototype will contain a single Burst Switch Element (BSE) with seven input and output ports. The BSE is being designed to support multistage configurations, allowing for systems with total capacities of tens of Tb/s. The data path portion of the BSE contains a 256 256 crossbar, which is bit-sliced in order to provide the required aggregate throughput of 256 Gb/s. The data path also includes a Burst Storage Unit which provides shared storage space for bursts that cannot be immediately switched through to the proper output channel. The BSU will provide 16 MB of aggregate storage capacity. The control portion of the BSE contains an ATM Switch Element (ASE), a set of seven Burst Processors (BP) and a Burst Storage Manager (BSM). These components collectively control the switching of bursts, including diverting bursts to the BSU as necessary.